Semiconductor devices including lower and upper device isolation patterns

ABSTRACT

In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.

CLAIM OF PRIORITY

The present application is a divisional of and claims priority from U.S.patent application Ser. No. 11/618,155, filed Dec. 29, 2006, whichclaims the benefit of Korean Patent Application No. 10-2006-075247,filed on Aug. 9, 2006, the disclosures of which are hereby incorporatedby reference herein in their entireties.

BACKGROUND

1. Field of Invention

Embodiments of the present invention described herein generally relateto semiconductor devices such as flash memory devices and methods offabricating the same.

2. Description of the Related Art

A typical semiconductor device is fabricated by forming device isolationlayers to define active regions in predetermined places of asemiconductor substrate and subsequently forming gate electrodescrossing over the active regions. The device isolation layers aregenerally formed after forming a trench mask pattern using a techniqueof shallow trench isolation (STI) that anisotropically etches thesemiconductor substrate under the trench mask pattern. The gateelectrodes are typically formed by depositing a gate insulation film anda gate conductive film in sequence on the active region and patterningthe gate conductive film to intersect the active region.

Meanwhile, a nonvolatile memory device such a flash memory device alsoincludes a floating gate electrode placed under the gate electrode.Forming the floating gate electrode is conducted generally using twopatterning steps with two mask patterns different from each other (i.e.,being arranged in directions parallel and vertical to the activeregion). In this process for forming the floating gate electrode, apatterning step is performed in the direction vertical to the activeregion to form the gate electrode. But, in the case of a patterning stepin the direction parallel to the active region, an expensivephotographic process is additionally needed, and a precise control ofphotographic processing parameters such as overlay characteristics isneeded.

With high integration density of semiconductor devices, it becomes moredifficult to regulate the parameters of photographic process.Accordingly, a way of patterning a floating gate conductive film inself-alignment has been proposed for replacing the patterning step basedon a photographic process.

FIGS. 1 through 3 are perspective views showing a general method offabricating a flash memory device.

Referring to FIG. 1, after forming a trench mask pattern 20 on asemiconductor substrate 10, trenches 15 are formed to define activeregions by using the trench mask pattern 20 as an etch mask. Here, thetrench mask pattern 20 may include lower and upper mask patterns 21 and22 which are stacked in sequence. The lower and upper mask patterns, 21and 22, are each used as a gate insulation film and a floating gateelectrode in a memory transistor of the flash memory device.

Next, a device isolation pattern 30 is formed to fill the trenches 15.The device isolation pattern 30 is formed by forming a device isolationlayer to fill the trenches 15 and etching the device isolation layer toexpose the upper sidewalls of the upper mask pattern 22. In thisconventional art, the device isolation layer may be a silicon oxide filmformed by chemical vapor deposition (CVD). But, as well known, when agap region (e.g., the trench 15) with a large aspect ratio is filled upwith a layer form by CVD, discontinuous interfaces or voids aregenerated due to the step coverage characteristics of the CVD layer (see“Silicon Processing for the VLSI Era: Volume 1—Process Technology”written by Stanley Wolf, pp. 185 of 1990 edition, Lattice Press, and“Silicon Processing for the VLSI Era: Volume 2—Process Integration”written by Stanley Wolf, pp, 202 of 1990 edition by Lattice Press). Asthe device isolation pattern 30 is formed by etching the deviceisolation layer including the discontinuous interfaces or voids, a seam35 is formed at the upper center of the device isolation pattern 30 asshown in FIG. 1.

Referring to FIG. 2, an intergate insulation film 40 and a control gatefilm 50 are sequentially deposited on the resultant structure includingthe device isolation pattern 30, Referring to FIG. 3, the intergateinsulation film 40, the control gate film 50, and the upper mask pattern22 are patterned to form gate lines crossing over the active regions.The gate line is composed of an intergate insulation pattern 45, acontrol gate electrode 55, and a floating gate electrode 25 interposedbetween the intergate insulation pattern 45 and the active region, whichare sequentially stacked with crossing over the active regions.

As shown in FIG. 3, the intergate insulation film 40 and the controlgate film 50 may be formed to fill the seam 35. But, the control gatefilm 50 formed in the seam 35 may remain therein without being etchedaway clearly. Such remaining portions of the control gate film 50 in theseam 35 can act as electrical paths 99 causing undesirable bridgesbetween adjacent gate lines and, as a result, yield a defective product.

SUMMARY

Embodiments of the present invention provide a method of fabricating asemiconductor device such as a flash memory device capable of preventingbridges between adjacent gate lines. Embodiments of the presentinvention also provide flash memory devices capable of preventingbridges between adjacent gate lines.

One embodiment exemplarily described herein can be characterized as amethod of fabricating a flash memory device that includes forming atrench mask pattern, the trench mask pattern comprising a gateinsulation pattern and a charge storage pattern; etching thesemiconductor substrate using the trench mask pattern as an etch maskthereby forming trenches defining active regions; sequentially forming alower isolation pattern and an upper device isolation pattern in thetrench; sequentially forming an intergate insulation film and a controlgate film on the upper device isolation pattern; and patterning thecontrol gate film, the intergate insulation film and the charge storagepattern to form gate lines crossing over the active regions.

In one embodiment, the lower device isolation pattern may be formed byforming a lower device isolation layer to fill the trench and etchingthe lower device isolation layer until exposing upper sidewalls of thetrench. During this process, the lower device isolation layer mayinclude silicon oxide and be formed by a process such as chemical vapordeposition. Further, the lower device isolation layer may be formed by aprocess in which successive steps of film deposition and etching areperformed at least once.

In one embodiment, the structure including the lower device isolationlayer may be thermally treated at a temperature of about 500° C. toabout 900° C. before forming the upper device isolation pattern. Thethermal treatment may be carried out in an ambient containing at leastone of nitrogen, argon, oxygen, and water vapor under pressure of about10 Torr to about 760 Torr.

In one embodiment, the upper device isolation pattern can be formed byforming an upper device isolation layer on the lower device isolationpattern and etching the upper device isolation layer until uppersidewalls of the trench mask pattern are exposed. The upper deviceisolation layer may include a high-density plasma silicon oxide film.The high-density plasma silicon oxide film may be formed according to ahigh-density plasma deposition process whereby film deposition andetching are simultaneously conducted. The high-density plasma depositionprocess may use processing gas with at least one of helium and hydrogen.

In one embodiment, a thermal oxide film may be formed on an inner wallof the trench by means of thermal oxidation before forming the lowerdevice isolation pattern. In addition, a nitride liner may be furtherformed on the thermal oxide film before forming the lower deviceisolation pattern.

In one embodiment, the gate line may include a charge storage electrode,an intergate insulation pattern and a control gate electrode, which arestacked in sequence. The intergate insulation pattern and the controlgate electrode are stacked in sequence and cross over the activeregions. The charge storage electrode is interposed between the activeregion and the intergate insulation pattern. Further, the intergateinsulation pattern directly contacts the upper device isolation patternover the trench.

In one embodiment, the charge storage electrode includes polysilicon andthe intergate insulation pattern includes at least one of silicon oxide,silicon nitride, silicon oxynitride, and high-dielectric material. Thecontrol gate electrode includes at least one of polysilicon, metalsilicide, and metal.

In one embodiment, the charge storage pattern, after being used as anetch mask in forming the trench, turns into the charge storage electrodewhile forming the gate line.

In one embodiment, spacers may be further formed on both sidewalls ofthe trench mask pattern before forming the intergate insulation film. Inthis case, the upper device isolation pattern may be etched using thespacers as an etch mask, thereby forming a recess region before formingthe intergate insulation film, A bottom surface of the recess region maybe lower than a bottom surface of the spacers and higher than a topsurface of the lower device isolation pattern.

Another embodiment exemplarily described herein can be characterized asa flash memory device that includes a semiconductor substrate includingtrenches defining active regions; lower and upper device isolationpatterns disposed in the trench; an intergate insulation pattern and acontrol gate electrode disposed on the semiconductor substrate to crossover the active regions; a charge storage electrode between the controlgate electrode and the active region; and a gate insulation patternbetween the charge storage electrode and the active region, wherein theintergate insulation pattern directly contacts the upper deviceisolation pattern between the active regions.

In one embodiment, the lower device isolation pattern may includesilicon oxide formed by a chemical vapor deposition process, and theupper device isolation pattern may include silicon oxide formed by ahigh-density plasma deposition process. Further, the lower deviceisolation pattern includes a discontinuous interface extending toward abottom of the trench from a top center of the lower device isolationpattern, and the upper device isolation pattern covers the discontinuousinterface of the lower device isolation pattern.

In one embodiment, spacers may be disposed at both sidewalls of thecharge storage electrode under the intergate insulation pattern. Here,the spacers expose a top surface of the upper device isolation pattern.In addition, the upper device isolation pattern may include a recessregion formed between the spacers. In this case, a bottom of the recessregion is leveled lower than a bottom of the spacers and higher than atop of the lower device isolation pattern.

Still another embodiment exemplarily described herein can becharacterized as a memory device that includes a semiconductor substrateincluding trenches defining active regions; a lower device isolationpattern in the trench, wherein a void is defined within the lower deviceisolation pattern; an upper device isolation pattern in the trench andon the lower device isolation pattern, wherein the upper deviceisolation pattern extends substantially contiguously between the activeregions from an upper surface of the upper device isolation pattern to alower surface of the upper device isolation pattern; an intergateinsulation pattern and a control gate electrode disposed on thesemiconductor substrate to cross over the active regions; a chargestorage electrode between the control gate electrode and the activeregion; and a gate insulation pattern between the charge storageelectrode and the active region.

A further understanding of the nature and advantages of the presentinvention herein may be realized by reference to the remaining portionsof the specification and the attached drawings.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying figures are included to provide a further understandingof the present invention, and are incorporated in and constitute a partof this specification. The drawings illustrate exemplary embodiments ofthe present invention and, together with the description, serve toexplain principles of the present invention. In the figures:

FIGS. 1 through 3 are perspective views showing a conventional method offabricating a flash memory device;

FIGS. 4-11 are perspective views illustrating one embodiment of a methodof fabricating a flash memory device; and

FIG. 12 is a sectional view illustrating an exemplary embodiment of aflash memory device.

DETAILED DESCRIPTION

Embodiments of the present invention will be exemplarily described belowin more detail with reference to the accompanying drawings. Theseembodiments may, however, be realized in different forms and should notbe constructed as limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure will be thoroughand complete, and will fully convey the scope of the present inventionto those skilled in the art.

In the figures, the dimensions of layers and regions are exaggerated forclarity of illustration. It will also be understood that when a layer(or film) is referred to as being ‘on’ another layer or substrate, itcan be directly on the other layer or substrate, or intervening layersmay also be present. Further, it will be understood that when a layer isreferred to as being ‘under’ another layer, it can be directly under,and one or more intervening layers may also be present. In addition, itwill also be understood that when a layer is referred to as being‘between’ two layers, it can be the only layer between the two layerS,or one or more intervening layers may also be present.

Moreover, the description hereinbelow uses terms of first, second, orthird for representing pluralities of various regions or films, thoseterms are employed to differentiate one from another, not restrictivethereto. In a certain case, a first region or film may be referred to asa second region or film in another embodiment. And, embodimentsdescribed herein may include their complementary cases. In the figures,like reference numerals refer to like elements throughout.

Hereinafter, it will be described about an exemplary embodiment of thepresent invention in conjunction with the accompanying drawings.

FIGS. 4-11 are perspective views illustrating one embodiment of a methodof fabricating a flash memory device.

Referring to FIG. 4, after arranging trench mask patterns 110 on asemiconductor substrate 100, the semiconductor substrate 100 isanisotropically etched by using the trench mask patterns 110 as an etchmask, forming trenches 105 to confine active regions.

According to one embodiment, the trench mask pattern 110 includes firstand second trench mask films 111 and 112. Here, the first trench maskfilm 111 may include a material such as silicon oxide formed, forexample, by thermal oxidation and the second trench mask film 112 mayinclude a material such as polysilicon. As illustrated, the first andsecond trench mask films, 111 and 112, remain after forming the trenches105 so that they may be used as a gate insulation film and a chargestorage film (e.g., a floating gate film) for cell transistors of asubsequently formed flash memory device.

According to another embodiment, the trench mask pattern 110 may furtherinclude a third trench mask film 113 on the second trench mask film 112.The third trench mask film 113 may include a material such as siliconnitride. According to still another embodiment, the trench mask pattern110, which includes silicon oxide and nitride materials, may be made upwith the first and third trench mask films 111 and 113. In this case,the trench mask pattern 110 may be removed after the etching process formaking the trenches 105.

Forming the trenches 105 can be carried out by anisotropically etchingthe semiconductor substrate 100 using an etch recipe having selectivityto the trench mask pattern 110. As a result, the active regionscorrespond with the area under the trench mask patterns 110 and thetrenches 105 are formed between the trench mask patterns 110.

Referring to FIG. 5, a process of thermal oxidation is carried out onthe resultant structure including the trenches 105, thereby forming athermal oxide film 120 on the inner walls of the trenches 105. Thisthermal oxidation contributes to curing physical damages that would begenerated on the inner walls during the former anisotropic etchingprocess.

According to one embodiment, a silicon nitride film 130 is conformablyformed on the resultant structure including the thermal oxide film 120.As well known, since the silicon nitride film 130 is formed in highdensity, it acts to intercept impurities from penetrating through theactive regions used for channel regions of transistors. During formationof the silicon nitride film 130, the thermal oxide film 120 blocks adirect contact between the silicon nitride film 130 and thesemiconductor substrate 100, thereby lessening stress due to adifference of thermal coefficient coefficients.

Next, referring to FIG. 6, a lower device isolation layer is formed onthe resultant structure including the silicon nitride film 130 byfilling the trenches 105. The lower device isolation layer may include amaterial such as silicon oxide and be formed according to a method suchas CVD. According to one embodiment, the lower device isolation layermay be formed in a single vapor deposition step. According to anotherembodiment, the lower device isolation layer may be formed in successivevapor deposition and etching steps, which may be repeated as desired.

In the meantime, as well known, when a gap region (e.g., the trench 105)with a large aspect ratio is filled up with a film by means of CVD, adiscontinuous interface 145 (e.g., a void, a seam, etc.) is generated,as shown in FIG. 6, due to the step coverage characteristics of such aCVD film. If the step coverage characteristics become too poor, voids(not shown) are formed by overhangs generated in the gap region.

The lower device isolation layer is etched using the trench maskpatterns 110 as an etch mask to form lower device isolation patterns 140exposing sidewalls of the trench mask patterns 110. The lower deviceisolation patterns 140 may be formed by etching and flattening (orplanarizing) the lower device isolation layer until the top surfaces ofthe trench mask patterns 110 is exposed. A chemical-mechanical polishing(CMP) technique may be used for the planarization process. Subsequently,the silicon nitride film 130 is etched to form a nitride liner 135interposed between the trench mask pattern 110 and the lower deviceisolation pattern 140.

Referring to FIG. 7, the lower device isolation layer is further etchedto form a lower device isolation pattern 140 having an upper surfacethat is lower than an upper surface of the active region. Accordingly,the lower device isolation pattern 140 may have an upper surface that issubstantially planar. During the further etching process, the lowerdevice isolation pattern 140 still contains the discontinuous interface145 extending toward the bottom of the trench 105.

As mentioned above, the third trench mask film 113 and the nitride liner135 may include a material such as silicon nitride. In this case, thethird trench mask film 113 and the nitride liner 135 have an etchingselectivity to the lower device isolation pattern 140. The nitride liner135 may be used as an etch mask, along with the trench mask pattern 110,for preventing damages during the etching process to form the lowerdevice isolation patterns 140.

According to one embodiment, a thermal treatment may be carried out onthe resultant structure including the lower device isolation patterns140. This thermal treatment may be conducted in a gas ambient containingat least one of nitrogen (N₂), argon (Ar), oxygen (O₂), and water vapor(H₂O), with the temperature of about 500° C. to about 900° C., under apressure of about 10 Torr to about 760 Torr. The lower device isolationpattern 140 may be densified upon performing the thermal treatment.

Referring to FIG. 8, an upper device isolation layer 150 is formed onthe resultant structure including the lower device isolation patterns140. According to one embodiment, the upper device isolation layer 150may include a material such as an oxide and be formed according to ahigh-density plasma (HDP) deposition process. A CMP process is thencarried out to etch the upper device isolation layer 150 and expose thetops of the trench mask patterns 110.

In the aforementioned HDP process, film deposition occurs simultaneouslywith etching of the film, but the deposition rate is faster than theetching rate. Because film deposition occurs simultaneously with etchingof the film, HDP processes are different from alternately conducting thefilm deposition and etching steps (i.e., the process used to form thelower device isolation layer). Moreover, because film deposition andetching steps of HDP processes are carried out in the same reactionchamber, HDP processes are differentiated from processes of forming thelower device isolation layer by alternately conducting film depositionand etching steps in different reaction chambers. Due the manner inwhich the HDP oxide layer is formed, the upper device isolation layer150 does not have a discontinuous interface generating seams. Such astructure is different from the lower device isolation pattern 140.

During the HDP process, depositing and sputtering gases for depositingand etching the upper device isolation layer 150 flow into the samechamber. According to one embodiment, the depositing gas may contain atleast one of silane (SiH₄) gas, disilane (Si₂H₄) gas, and oxygen gas.The sputtering gas may contain at least one of hydrogen gas, helium gas,and argon gas.

According to another embodiment, the upper device isolation layer 150may be formed by repeating the HDP process several times. In this case,the step of etching the upper device isolation layer 150 may be carriedout after completing the HDP process.

Referring to FIG, 9, using the trench mask pattern 110 (i.e., the thirdtrench mask film 113) and the nitride liner 135 as an etch mask, theupper device isolation layer 150 is selectively etched to form upperdevice isolation patterns 155 on the lower device isolation patterns140. Because the upper device isolation layer 150 was subject to a CMPprocess, an upper surface of the upper device isolation pattern 155 maybe substantially planar.

According to one embodiment, an upper surface of the upper deviceisolation pattern 155 may be lower than the second trench mask film 112and higher than the first trench mask film 111. According to anotherembodiment, an upper surface of the upper device isolation pattern 155may be lower than the upper surface of the active region (as shown inFIG. 9).

The third trench mask film 113 is then removed by means of an etchingrecipe having selectivity to the upper device isolation pattern 155. Theetching step for removing the third trench mask film 113 may be carriedout by a technique such as wet etching. During this, sidewalls of thenitride liner 135, which are exposed on the upper device isolationpatterns 155, may be removed along with the third trench mask film 113.

Referring to FIG. 10, an intergate insulation film 160 and a controlgate film 170 are then deposited in sequence on the resultant structureincluding the upper device isolation patterns 155. As a result, theintergate insulation film 160 directly contacts the upper deviceisolation patterns 155 in the trenches 105.

According to one embodiment, the intergate insulation film 160 includesat least one of a silicon oxide, a silicon nitride, a silicon oxynitrideand a high-dielectric layer. The control gate film 170 includes at leastone of a polysilicon, a metal silicide and a metal layer. For instance,the intergate insulation film 160 may include a silicon oxide layer, asilicon nitride layer and a silicon oxide layer stacked in sequence. Thecontrol gate film 170 may, for example, include lower and upper controlgate films 171 and 172 which are stacked in sequence. The lower controlgate film 171 may include, for example, polysilicon while the uppercontrol gate film 172 may include, for example, tungsten silicide.

Referring to FIG, 11, the control gate film 170, the intergateinsulation film 160 and the first and second trench mask films 111 and112, respectively, are patterned to form gate lines crossing over theactive regions. Namely, the gate line is formed of a charge storageelectrode 117 (e.g., a floating gate electrode), an intergate insulationpattern 165, and a control gate electrode 175 which are stacked insequence. The first trench mask film 111 is patterned to form gateinsulation film 116. Forming the gate lines can be carried out byanisotropically etching the control gate film 170 with an etch recipehaving a selectivity to the intergate insulation film 165, etching theintergate insulation film 150 to expose the second trench mask film 112and then anisotropically etching the second trench mask film 112 with anetch recipe having a selectivity to silicon oxide.

During this, the charge storage electrode 117 is formed by patterningthe second trench mask film 112, previously used as the etch mask forthe trenches, and is self-aligned on the active region. The intergateinsulation patterns 165 cross over the active regions and the upperdevice isolation patterns 155, covering the top and sidewalls of thecharge storage electrode 117. Because the upper device isolationpatterns 155 contact both the intergate insulation patterns 165 and thelower device isolation patterns 140, it is possible to prevent technicalproblems caused by the discontinuous interface 145 of the lower deviceisolation patterns 140. The control gate electrode 175 results frompatterning the lower and upper gate films 171 and 172, being composed oflower and upper control gate electrodes 176 and 177.

FIG. 12 is a sectional view illustrating an exemplary embodiment of aflash memory device.

Referring to FIGS. 9 and 12, before forming the intergate insulationfilm 160, spacers 119 may be formed at both sidewalls of trench maskpatterns 110′. The spacers 119 may be formed on the resultant structureincluding the upper device isolation patterns 155. Next, using thespacers 119 and the trench mask patterns 110′ as an etch mask, theexposed top surfaces of the device isolation patterns 155 are etched toform recess regions 200 having a bottom surface lower than the topsurfaces of the active regions.

The subsequent processing steps after forming the recess regions 200 aresame as those exemplarily described above with respect to FIGS. 4-11.Forming the recess regions 200 as shown in FIG. 12 allows the controlgate electrode 175 to be extended toward the bottoms of the trenches105. This extended control gate electrode 175 can be used as a shieldinglayer, contributing to reducing electrical interference between adjacentmemory cells.

As described above, the HDP process is used to form the upper deviceisolation pattern on the lower device isolation pattern, formed by CVD.Thus, the upper device isolation pattern extends substantiallycontiguously between the active regions from an upper surface thereof toa lower surface thereof. Thus, the seam generable at the upper center ofthe lower device isolation pattern is covered by the upper deviceisolation pattern and bridges between adjacent gate lines, which wouldotherwise be generated by filling the seam with the intergate insulationfilm and the control gate film as discussed above with respect to FIGS.1-3, can be prevented.

By forming the charge storage electrode in self-alignment, an aspectratio of a gap region made by the trench mask patterns and the trenchesincreases to deepen the problems due to the gate bridges and the seam.But, those technical problems can be prevented effectively by thepresent invention that provides the way of covering the seam by the HDPfilm.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the present invention. Thus, to the maximumextent allowed by law, the scope of the present invention is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

1. A semiconductor device comprising: a semiconductor substrate including trenches defining active regions; lower and upper device isolation patterns disposed in the trenches; an intergate insulation pattern and a control gate electrode disposed on the semiconductor substrate to cross over the active regions; a charge storage electrode between the control gate electrode and the active regions; and a gate insulation pattern between the charge storage electrode and the active regions, wherein the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.
 2. The device of claim 1, wherein the lower device isolation pattern is a chemically vapor deposited silicon oxide film and the upper device isolation pattern is a high-density plasma silicon oxide film.
 3. The device of claim 1, wherein the lower device isolation pattern includes a discontinuous interface extending toward a surface of the semiconductor substrate from a surface of the lower device isolation pattern, and wherein the upper device isolation pattern covers the discontinuous interface.
 4. The device of claim 1, further comprising spacers disposed at sidewalls of the charge storage electrode under the intergate insulation pattern, wherein the spacers expose a top surface of the upper device isolation pattern.
 5. The device of claim 4, wherein the upper device isolation pattern comprises a recess region between the spacers, and wherein a bottom surface of the recess region is lower than a bottom surface of the spacers and higher than a top surface of the lower device isolation pattern.
 6. The device of claim 1, wherein an upper surface of the lower device isolation pattern is substantially planar.
 7. The device of claim 3, wherein the upper device isolation pattern is free of discontinuous interfaces.
 8. A semiconductor device comprising: a semiconductor substrate including trenches defining active regions; lower and upper device isolation patterns disposed in the trenches; an intergate insulation pattern and a control gate electrode disposed on the semiconductor substrate to cross over the active regions; a charge storage electrode between the control gate electrode and the active regions; and a gate insulation pattern between the charge storage electrode and the active regions, wherein the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions, wherein the lower device isolation pattern includes a discontinuous interface extending toward a surface of the semiconductor substrate from a surface of the lower device isolation pattern, and wherein the upper device isolation pattern covers the discontinuous interface.
 9. A semiconductor device comprising: a semiconductor substrate including trenches defining active regions; lower and upper device isolation patterns disposed in the trenches; an intergate insulation pattern and a control gate electrode disposed on the semiconductor substrate to cross over the active regions; a charge storage electrode between the control gate electrode and the active regions; and a gate insulation pattern between the charge storage electrode and the active regions, wherein the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions, wherein the lower device isolation pattern includes a discontinuous interface extending toward a surface of the semiconductor substrate from a surface of the lower device isolation pattern, wherein the upper device isolation pattern covers the discontinuous interface, and wherein the upper device isolation pattern is free of discontinuous interfaces. 